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SN74HCS164 データシート(PDF) 9 Page - Texas Instruments

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部品番号. SN74HCS164
部品情報  SN74HCS164 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs
ダウンロード  24 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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SN74HCS164 Datasheet(HTML) 9 Page - Texas Instruments

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8 Detailed Description
8.1 Overview
The SN74HCS164 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well
as an asynchronous clear (CLR). The device requires a high signal on both A and B in order to set the input data
line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK
is high or low, provided that the minimum set-up time requirements are met.
The CLK pin of the SN74HCS164 is rising-edge triggered, activating on the transition from LOW to HIGH. Upon
a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and
propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each
clock trigger. If a low signal is applied to the CLR pin, then the SN74HCS164 will set all registers to a logical low
value immediately.
8.2 Functional Block Diagram
CLK
CLR
A
B
D
R
D
R
D
R
D
R
D
R
D
R
D
R
D
R
QA
QB
QC
QD
QE
QF
QG
QH
8
1
2
9
3
4
5
6
10
11
12
13
Q
Q
Q
Q
Q
Q
Q
Q
Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS164
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
www.ti.com
SN74HCS164
SCLS827 – AUGUST 2020
Copyright © 2020 Texas Instruments Incorporated
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