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SN74HCS164 データシート(PDF) 14 Page - Texas Instruments

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部品番号. SN74HCS164
部品情報  SN74HCS164 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs
ダウンロード  24 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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SN74HCS164 Datasheet(HTML) 14 Page - Texas Instruments

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9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS164
to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
CLK
A
B
CLR
QA
QB
QC
QD
QE
QF
QG
QH
Clear
Clear
Figure 9-2. Application Timing Diagram
SN74HCS164
SCLS827 – AUGUST 2020
www.ti.com
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