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SN74HCS244-Q1 データシート(PDF) 8 Page - Texas Instruments

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部品番号. SN74HCS244-Q1
部品情報  SN74HCS244-Q1 Automotive Octal Buffers and Line Drivers With Schmitt-Trigger Inputs and 3-State Outputs
ダウンロード  18 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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SN74HCS244-Q1 Datasheet(HTML) 8 Page - Texas Instruments

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8 Detailed Description
8.1 Overview
The SN74HCS244-Q1 contains 8 individual high speed CMOS buffers with Schmitt-trigger inputs and 3-state
outputs.
Each buffer performs the boolean logic function xYn = xAn, with x being the bank number and n being the
channel number.
Each output enable (xOE) controls four buffers. When the xOE pin is in the low state, the outputs of all buffers in
the bank x are enabled. When the xOE pin is in the high state, the outputs of all buffers in the bank x are
disabled. All disabled output are placed into the high-impedance state.
To ensure the high-impedance state during power up or power down, both OE pins should be tied to VCC through
a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver
and the leakage of the pin as defined in the Electrical Characteristics table.
8.2 Functional Block Diagram
xA2
xA3
xA4
One of Two 4-Bit Bus Buffers
xA1
xOE
xY1
xY2
xY3
xY4
Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS244-Q1
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
SN74HCS244-Q1
SCLS821 – JULY 2020
www.ti.com
8
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