SN74HCS244-Q1 データシート(PDF) 11 Page - Texas Instruments
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SN74HCS244-Q1 Datasheet(HTML) 11 Page - Texas Instruments
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The maximum junction temperature, T
listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
184.108.40.206 Input Considerations
Input signals must cross V
to be considered a logic LOW, and V
to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either V
or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS244-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS244-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔV
in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than V
or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
220.127.116.11 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the V
specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the V
specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to V
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from V
to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the V
and GND pins. An example layout is shown in the Layout
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS244-Q1 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (V
) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
SCLS821 – JULY 2020
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