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TLV9151 データシート(PDF) 33 Page - Texas Instruments |
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TLV9151 データシート(HTML) 33 Page - Texas Instruments |
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33 / 61 page  33 TLV9151, TLV9152, TLV9154 www.ti.com SBOS986B – OCTOBER 2019 – REVISED MAY 2020 Product Folder Links: TLV9151 TLV9152 TLV9154 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated 9 Power Supply Recommendations The TLV915x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 16 V can permanently damage the device; see the Absolute Maximum Ratings. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As illustrated in Figure 54, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. |
同様の部品番号 - TLV9151_V02 |
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同様の説明 - TLV9151_V02 |
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