Preliminary

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FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction

FIGURE 11. 8-Bit Camera Interface (10MHz to 30MHz Parallel Operation)

Figure shows an 8-bit LCD Interface with VSYNC/HSYNC

capability. This interface is a very straightforward in imple-

menting the

PSerDes devices. Note that two additional

data bits are still available for implementing additional data

bits or control signals.

Figure shows an application for a camera interface for a

flip phone using the FIN12AC. For this application the ref-

erence clock is generated on the baseband side of the flip

and passed across the SerDes pair differentially. This sig-

nal is then reconverted to a single ended signal for use as

a reference clock by the imager. For some applications it

may be possible to connect the REFCK directly to the

CKREF signal of the FIN12AC serializer.