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ADC3664 データシート(PDF) 32 Page - Texas Instruments |
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ADC3664 データシート(HTML) 32 Page - Texas Instruments |
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32 / 71 page  Normalized Frequency (Fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -120 -100 -80 -60 -40 -20 0 Decb Passband Transition Band Alias Band Attn Spec Figure 8-27. Decimation by 16 complex frequency response Normalized Frequency (Fs) 0 0.003 0.006 0.009 0.012 0.015 0.018 0.021 0.024 0.027 0.03 -0.2 -0.19 -0.18 -0.17 -0.16 -0.15 -0.14 -0.13 -0.12 -0.11 -0.1 Decb Passband Transition Band Alias Band Attn Spec Figure 8-28. Decimation by 16 complex passband ripple response Normalized Frequency (Fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -120 -100 -80 -60 -40 -20 0 Decb Passband Transition Band Alias Band Attn Spec Figure 8-29. Decimation by 32 complex frequency response Normalized Frequency (Fs) 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 -0.25 -0.245 -0.24 -0.235 -0.23 -0.225 -0.22 -0.215 -0.21 -0.205 -0.2 Decb Passband Transition Band Alias Band Attn Spec Figure 8-30. Decimation by 32 complex passband ripple response 8.3.4.6 SYNC The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/ SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is latched in by the rising edge of the sampling clock as shown in Figure 8-31. CLK tS,SYNC tH,SYNC SYNC Figure 8-31. External SYNC timing diagram The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks as well as I and Q data within the same sample. If no SYNC signal is given the internal clock dividers will not be synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit). When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is an integer. This ensures phase continuity of the clock divider. ADC3664 SBAS888 – DECEMBER 2020 www.ti.com 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3664 |
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同様の説明 - ADC3664 |
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