ADC3683 datasheet(39/73 Pages) TI

部品番号	ADC3683

部品情報	ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

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8.3.5.2.1 Configuration Example

The following is a step by step programming example to configure the ADC368x to complex decimation by 8 with

1-wire SLVDS and 16-bit output.

1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire SLVDS)

2. 0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)

3. 0x19 0x80 (configure FCLK)

4. 0x1B 0x88 (select 16-bit output resolution)

5. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)

6. 0x24 0x06 (enable decimation filter)

7. 0x25 0x30 (configure complex decimation by 8)

8. 0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency)

9. 0x27/0x2E 0x08 (configure Q-delay register bit)

10.0x26 0xAA, 0x26 0x88 (set digital mixer gain to 6-dB and toggle the mixer update)

8.3.5.3 Output Data Format

The output data can be configured to two's complement (default) or offset binary formatting using SPI register

writes (register 0x8F and 0x92). Table 8-8 provides an overview for minimum and maximum output codes for the

two formatting options. The actual output resolution is set by the output bit mapper.

Table 8-8. Overview of minimum and maximum output codes vs output resolution for different formatting

Two's Complement (default)

Offset Binary

RESOLUTION (BIT)

14

16

18

20

14

16

18

20

VIN,MAX

0x1FFF

0x7FFF

0x1FFFF

0x7FFFF

0x3FFF

0xFFFF

0x3FFFF

0xFFFFF

0

0x0000

0x00000

0x2000

0x8000

0x20000

0x80000

VIN,MIN

0x2000

0x8000

0x20000

0x80000

0x0000

0x00000

8.3.6 Test Pattern

In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled

via SPI register writes (0x14/0x15/0x16). In decimation mode (real and complex), the test patterns replace the

output data of the DDC - however channel A controls the test patterns for both channels.

• RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native

resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in

RAMP pattern mode.

– 00001: 18-bit output resolution

– 00100: 16-bit output resolution

– 10000: 14-bit output resolution

• Custom Pattern: Configured in the CUSTOM PAT register

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ADC3683

SBAS872 – DECEMBER 2020

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同様の部品番号 - ADC3683

メーカー	部品番号	データシート	部品情報
Texas Instruments	ADC3683	4Mb / 75P	[Old version datasheet] ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC
	ADC3683	4Mb / 75P	[Old version datasheet] ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC DECEMBER 2021
	ADC3683	5Mb / 85P	[Old version datasheet] ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC REVISED OCTOBER 2022
	ADC3683	3Mb / 70P	[Old version datasheet] ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC MARCH 2024
	ADC3683-SP	3Mb / 70P	[Old version datasheet] ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC MARCH 2024

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同様の説明 - ADC3683

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Texas Instruments	ADC3682	4Mb / 75P	[Old version datasheet] ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC DECEMBER 2021
	ADC3681	5Mb / 85P	[Old version datasheet] ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC REVISED OCTOBER 2022
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	ADC3662	4Mb / 75P	[Old version datasheet] ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power, Dual-Channel ADC DECEMBER 2021
	ADC3661	5Mb / 86P	[Old version datasheet] ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power, Dual-Channel ADC REVISED SEPTEMBER 2022
	ADC3661	5Mb / 86P	[Old version datasheet] ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power, Dual-Channel ADC REVISED SEPTEMBER 2022
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