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BQ25672 データシート(PDF) 39 Page - Texas Instruments

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部品番号 BQ25672
部品情報  BQ25672 I2C Controlled, 1-4 Cell, 3-A Buck Battery Charger with Dual-Input Selector and Integrated ADC
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

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8.3.13.2 START and STOP Conditions
All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
START (S)
STOP (P)
SDA
SCL
SDA
SCL
Figure 8-15. START and STOP Conditions on the I2C Bus
8.3.13.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most
Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, it can hold the SCL line low to force the master into a wait state (clock
stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL
line.
SCL
SDA
START or
Repeated
START
S or Sr
1
2
7
8
9
MSB
ACK
Acknowledgement
signal from slave
1
2
8
9
ACK
Acknowledgeme
nt signal from
receiver
STOP or
Repeate
d START
P or Sr
Figure 8-16. Data Transfer on the I2C Bus
8.3.13.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte
was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock
pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this 9th clock pulse.
A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The master can then generate
either a STOP to abort the transfer or a repeated START to start a new transfer.
8.3.13.5 Slave Address and Data Direction Bit
After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/ W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1101 011' (0x6B) by default. The address bit arrangement is shown below.
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BQ25672
SLUSEB9 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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