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TMS320F28335 データシート(PDF) 54 Page - Texas Instruments

部品番号 TMS320F28335
部品情報  TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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TMS320F28335 データシート(HTML) 54 Page - Texas Instruments

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tw(WAKE-INT)
td(WAKE-STBY)
td(IDLE−XCOL)
Wake-up
Signal(G)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
STANDBY
Normal Execution
STANDBY
Flushing Pipeline
(A)
(B)
(C)
(D)
(E)
(F)
Device
Status
54
TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439O – JUNE 2007 – REVISED APRIL 2019
www.ti.com
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Product Folder Links: TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235
TMS320F28234 TMS320F28232
Specifications
Copyright © 2007–2019, Texas Instruments Incorporated
A.
IDLE instruction is executed to put the device into STANDBY mode.
B.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail. It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
C.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D.
The external wake-up signal is driven active.
E.
After a latency period, the STANDBY mode is exited.
F.
Normal execution resumes. The device will respond to the interrupt (if enabled).
G.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-12. STANDBY Entry and Exit Timing Diagram


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