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TMS320F280049 データシート(PDF) 93 Page - Texas Instruments |
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TMS320F280049 データシート(HTML) 93 Page - Texas Instruments |
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93 / 231 page  OSCCLK XCLKOUT HALT HALT Flushing Pipeline Device Status Normal Execution GPIOn (A) (C) (D)(E) (F) (B) (G) t d(IDLE-XCOS) t w(WAKE-GPIO) t d(WAKE-HALT) Oscillator Start-up Time 93 TMS320F280049, TMS320F280049C TMS320F280048, TMS320F280048C, TMS320F280045 TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C www.ti.com SPRS945E – JANUARY 2017 – REVISED APRIL 2020 Submit Documentation Feedback Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C Specifications Copyright © 2017–2020, Texas Instruments Incorporated A. IDLE instruction is executed to put the device into HALT mode. B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly. C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be taken to maintain a low noise environment before entering and during HALT mode. E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now exited. G. Normal operation resumes. H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock. Figure 5-27. HALT Entry and Exit Timing Diagram |
同様の部品番号 - TMS320F280049_V02 |
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同様の説明 - TMS320F280049_V02 |
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