AP0201AT datasheet(24/31 Pages) ONSEMI

部品番号	AP0201AT

部品情報	AP0201AT High-Dynamic Range (HDR) Image Signal Processor (ISP)

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AP0201AT

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I/O TIMING

MII I/O Timing

TX_CLK

TXD

tsetup_txd

thold_txd

RX_CLK

RXD

tsetup_rxd

thold_rxd

Figure 13. MII I/O Timing Diagram

Table 13. MII I/O TIMING CHARACTERISTICS

Symbol

Parameter

Conditions

Min

Max

Unit

Freq

TX_CLK and RX_CLK Input clocks

1.8 V to 3.3 V, 25 pF load

25−110 ppm

25+110 ppm

MHz

tsetup_txd

TXD[3:0], TX_ERR, TX_EN, setup to

TX_CLK input rise

1.8 V to 3.3 V, 25 pF load

15.0

ns

thold_txd

TXD[3:0], TX_ERR, TX_EN hold from

TX_CLK input rise

1.8 V to 3.3 V, 25 pF load

2.0

ns

tsetup_rxd

RXD[3:0], RX_ERR, CRS_DV setup to

RX_CLK input rise

1.8 V to 3.3 V

8.0

ns

thold_rxd

RXD[3:0], RX_ERR, CRS_DV hold from

RX_CLK input rise

1.8 V to 3.3 V

8.0

ns

同様の部品番号 - AP0201AT

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