データシートサーチシステム |
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74LVC125AM データシート(PDF) 1 Page - STMicroelectronics |
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74LVC125AM データシート(HTML) 1 Page - STMicroelectronics |
1 / 9 page 1/9 February 2002 s 5V TOLERANT INPUTS s HIGH SPEED: tPD = 4.8ns (MAX.) at VCC =3V s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 24mA (MIN) at VCC =3V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LVC125A is a low voltage CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. It can be interfaced to 5V signal environment for inputs in mixed 3.3/5V system. These devices require the same 3-STATE control input G to be taken high to make the output go in to the high impedance state. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVC125A LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) HIGH PERFORMANCE PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R SOP 74LVC125AM 74LVC125AMTR TSSOP 74LVC125ATTR TSSOP SOP |
同様の部品番号 - 74LVC125AM |
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同様の説明 - 74LVC125AM |
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