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FOD0708R1 データシート(PDF) 3 Page - Fairchild Semiconductor |
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FOD0708R1 データシート(HTML) 3 Page - Fairchild Semiconductor |
3 / 11 page 3 www.fairchildsemi.com FOD0708/FOD0738 Rev. 1.0.6 Switching Characteristics Over recommended temperature (TA = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25°C, VDD = +5 V. *All typicals at TA = 25°C and VDD = 5V unless otherwise noted. Isolation Characteristics (TA = -40°C to +100°C Unless otherwise specified.) ** All typical values are at VCC = 5 V, TA = 25°C Notes: 1. Propagation delay time, high to low (tPHL), is measured from the 50% level on the rising edge of the input pulse to the 2.5V level of the falling edge of the output voltage signal. Propagation delay time, low to high (tPLH), is measured from the 50% level on the falling edge of the input pulse to the 2.5V level of the rising edge of the output voltage signal. 2. Pulse width distoration is defined as the absolute difference between the high to low and low to high propagation delay times, | tPHL – tPLH |. 3. Propagation delay skew, tPSK, is defined as the worst case difference in tPHL or tPLH between units within the recommended operating range of the device. 4. CMH – The maximum tolerated rate of rise of the common mode voltage to ensure the output will remain in the high state, (i,e., VOUT > 2.0V) Measured in kilovolts per microsecond (kV/µs). 5. CML – The maximum tolerated rate of fall of the common mode voltage to ensure the output will remain in the low state, (i,e., VOUT < 0.8V). Measured in kilovolts per microsecond (kV/µs). 6. Isolation voltage, VISO, is an internal device dielectric breakdown rating. For this test, pins 1,2,3,4 are common, and pins 5,6,7,8 are common. Symbol Parameter Test Conditions Min. Typ.* Max. Units tPHL Propagation Delay Time to Logic Low Output IF = 12 mA, CL = 15 pF CMOS Signal Levels, note 1, fig. 10 20 60 ns tPLH Propagation Delay Time to Logic High Output IF = 12 mA, CL = 15 pF CMOS Signal Levels, note 1, fig. 10 FOD0708 13 60 ns FOD0738 11 60 PW Pulse Width 100 ns | PWD | Pulse Width Distortion IF = 12 mA, CL = 15 pF CMOS Signal Levels, note 2 0 30 ns tPSK Propagation Delay Skew IF = 12 mA, CL = 15 pF CMOS Signal Levels, note 3 40 ns tR Output Rise Time (10%–90%) IF = 12 mA, CL = 15 pF CMOS Signal Levels 12 ns tF Output Fall Time (90%–10%) IF = 12 mA, CL = 15 pF CMOS Signal Levels 8 ns | CMH | Common Mode Transient Immunity at Logic High Output VCM = 1000 V, TA = 25°C, IF = 0 mA, note 4, fig. 11 25 50 kV/µs | CML | Common Mode Transient Immunity at Logic Low Output VCM = 1000 V, TA = 25°C, IF = 12 mA, note 5, fig. 11 25 50 kV/µs Characteristics Test Conditions Symbol Min Typ.** Max Unit Input-Output Insulation Leakage Current (Relative humidity = 45%) (TA = 25°C, t = 5 s) (VI-O = 3000 VDC) (Note 6) II-O 1.0 µA Withstand Insulation Test Voltage (II-O ≤ 10 µA, RH < 50%, TA = 25°C) (t = 1 min.) (Note 6) VISO 2500 VRMS Resistance (Input to Output) (VI-O = 500 V) (Note 6) RI-O 1012 Ω Capacitance (Input to Output) (f = 1 MHz) (Note 6) CI-O 0.6 pF |
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