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KM681000EL-L データシート(PDF) 8 Page - Samsung semiconductor

部品番号 KM681000EL-L
部品情報  128Kx8 bit Low Power CMOS Static RAM
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メーカー  SAMSUNG [Samsung semiconductor]
ホームページ  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM681000EL-L データシート(HTML) 8 Page - Samsung semiconductor

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CMOS SRAM
KM681000E Family
Revision 1.01
December 1999
8
DATA RETENTION WAVE FORM
CS1 controlled
VCC
4.5V
2.2V
VDR
CS1
GND
Data Retention Mode
CS
≥VCC - 0.2V
tSDR
tRDR
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
CS2
tCW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
tCW(2)
tWR(4)
tWP(1)
tDW
tDH
tAS(3)
tWC
CS2 controlled
VCC
4.5V
0.4V
VDR
CS2
GND
Data Retention Mode
tSDR
tRDR
CS2
≤0.2V


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