T E C H NI CA L INFO RMA T IO N
11
Functional Description – Mode 2
Serial Bus Operation
When OVRLD/SCL is tied to V5 to a 5 k
Ω resistor and the TA2021-100 senses this during power-
up it will go into Mode 2 operation, where control/status of the amplifier is by registers
accessed through a digital serial control bus. This serial bus is compatible with Philips’ I
2CTM bus.
The TA2021-100 operates as a slave device on the bus. The OVRLD/SCL line is an input (no clock
is generated by the TA2021-100) and the HMUTE/SDA line is a bi-directional serial data path.
Six simple operations with the two lines of the serial bus are used for transmitting to or
receiving from a TA2021-100:
1.
Start bit: A high-to-low transition of the data line while the clock line is in a high
state
2.
Seven-bit slave address: The first seven bits following a start bit (MSB first)
3.
Read/write bit which defines whether the slave is a transmitter or receiver: The next
bit immediately after the address is the direction of the transfer. A 0 indicates that
the master will write information to the slave. A 1 indicates that the master will
receive data from the slave.
4.
Acknowledge bit: Every eight-bit byte transferred (including the eight bits
comprising the address and read/write bit) is followed by an acknowledge bit from
the receiver (the master generates all clock pulses). The transmitter releases the
data line during the acknowledge clock pulse. If there was no error detected, the
receiver will pull down the SDA line during the high period of the acknowledge
clock pulse. If a slave receiver is not able to acknowledge, the slave will keep the
SDA line high and the master can then generate a stop bit to abort the transfer. If a
master receiver keeps the SDA line high during the acknowledge clock pulse the
master is signaling the end of data transmission and the slave transmitter releases
the data line to allow the master to generate a stop bit.
5.
Message bits divided into eight-bit bytes: One bit is transferred during each clock
pulse. The data must be stable during the high period of the clock. The data line
can only change when the clock line is low. The MSB of the byte is transmitted first.
6.
Stop bit: A low-to-high transition of the data line while the clock line is in a high
state.
Slave ID Address
The TA2021-100 has a seven-bit slave ID address. The five most-significant bits of the slave
address are hardwired inside the TA2021-100 and are 10000. The two least-significant bits are
determined by the voltage on the MIS/ADDR pin according to the following table:
MIS/ADDR Pin Voltage
(Fraction of V5)
Address
0.00 – 0.25
A1 = 0, A0 = 0
0.25 – 0.50
A1 = 0, A0 = 1
0.50 – 0.75
A1 = 1, A0 = 0
0.75 – 1.00
A1 = 1, A0 = 1
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