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ADS5242

SBAS330C – OCTOBER 2004 – REVISED OCTOBER 2005

ELECTRICAL CHARACTERISTICS (continued)

T

cycle, AVDD = 3.3V, LVDD = 3.3V, –1dBFS, I

channel, unless otherwise noted. All values are applicable after the device has been reset.

ADS5242

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUT

Differential Input Capacitance

4.0

pF

Analog Input Common-Mode Range

mV

Differential Input Voltage Range

Internal Reference

2.03

External Reference

2.03

× (VREF

3.0

CLK Cycles

–3dBFS, 25

Ω Series

Input Bandwidth

300

MHz

Resistances

DIGITAL DATA INPUTS

2.2

V

0.6

V

3.0

pF

DIGITAL DATA OUTPUTS

Data Format

Straight Offset Binary

Data Bit Rate

240

780

Mbps

SERIAL INTERFACE

SCLK Serial Clock Input Frequency

20

MHz

(7)

A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the

full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the

ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value

when the pulse is switched from ON (high) to OFF (low).

REFERENCE SELECTION

MODE

INT/EXT

DESCRIPTION

1

Default with internal pull-up.

Internal reference is powered down. The common-mode voltage

External Reference; FSR = 2.03

× (VREF

0

derived from the internal bandgap voltage.

5