データシートサーチシステム |
|
9354-00 データシート(PDF) 5 Page - Peregrine Semiconductor Corp. |
|
9354-00 データシート(HTML) 5 Page - Peregrine Semiconductor Corp. |
5 / 7 page Product Specification PE9354 Page 5 of 7 Document No. 70-0099-02 │ www.psemi.com ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Evaluation Kit Information Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE9354 SPDT switch. The RF common port is connected through a 50 Ω transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50 Ω transmission lines to the top two SMA connectors on the right side of the board, J2 and J3. A through transmission line connects SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and ε r of 4.4. J6 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device CNTL input. The fourth pin to the right (J2-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CTRL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. The ground plane has been removed from beneath the device for performance issues. It was found that insertion loss dips (suck-outs) were experienced due to the capacitive effect of the metal package sitting insulated by the solder-mask on the ground plane. All Figure 13. Evaluation Board Schematic Figure 12. Evaluation Board Layouts Peregrine specification 102/0129 data specified and shown on this datasheet was taken using this evaluation board configuration. For optimal performance, the package may be soldered directly to the ground plane, but the reliability issues associated with this mounting must be addressed by the customer. |
同様の部品番号 - 9354-00 |
|
同様の説明 - 9354-00 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |