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SN74HC74-Q1 データシート(PDF) 1 Page - Texas Instruments

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部品番号 SN74HC74-Q1
部品情報  DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

SN74HC74-Q1 データシート(HTML) 1 Page - Texas Instruments

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SN74HC74Q1
DUAL DTYPE POSITIVEEDGETRIGGERED FLIPFLOP
WITH CLEAR AND PRESET
SCLS577 − MARCH 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Qualification in Accordance With
AEC-Q100
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 15 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When
PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred
to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed
without affecting the levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40
°C to 125°C
SOIC − D
Reel of 2500
SN74HC74QDRQ1
HC74Q
−40
°C to 125°C
TSSOP − PW
Reel of 2000
SN74HC74QPWRQ1
HC74Q
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
LX
XL
H
L
LX
X
H†
H†
H
H
HH
L
H
H
LL
H
H
H
L
X
Q0
Q0
† This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
D OR PW PACKAGE
(TOP VIEW)
Copyright
 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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