3

®

DAC667

TIMING SPECIFICATIONS

SYMBOL

PARAMETER

MIN

TYP

MAX UNITS

Data Valid to End of CS

50

–

–

ns

Address Valid to End of CS

100

–

–

ns

CS Pulse Width

100

–

–

ns

Data Hold Time

0

–

–

ns

Output Voltage Settling Time

–

2

4

µs

ABSOLUTE MAXIMUM RATINGS

Digital Inputs (Pins 11–15, 17–28) to Power Ground ............. –1V to +7V

Ref In to Reference Ground ..............................................................

±12V

Bipolar Offset to Reference Ground .................................................

±12V

10V Span Resistor to Reference Ground .........................................

±12V

20V Span Resistor to Reference Ground .........................................

±24V

Power Dissipation ........................................................................ 1000mW

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

TEMPERATURE

LINEARITY ERROR

GAIN TC, max

PACKAGE DRAWING

PRODUCT

PACKAGE

RANGE

max at 25

(ppm/

DAC667JP

28-Pin Plastic DIP

0

°C to +70°C

±1/2LSB

±30

215

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

TIMING DIAGRAMS

Load first rank from Data Bus; A3 = 1.

t

Write Cycle #1

t

SETT

CS

±1/2LSB

A3

t

AC

t

CP

Load second rank from first rank; A2, A1, A0 = 1.

Write Cycle #2

Output

CS

A2–A0

t

AC

t

DC

t

DH

t

CP

DB11–DB0