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SMH4814SCR01 データシート(PDF) 5 Page - Summit Microelectronics, Inc. |
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SMH4814SCR01 データシート(HTML) 5 Page - Summit Microelectronics, Inc. |
5 / 44 page SMH4814 Preliminary Information Summit Microelectronics, Inc 2080 2.0 07/21/05 5 PIN DESCRIPTION (CONTINUED) Pin No. QFN Pin Type Name Description 18 I FEEDA Connect to the -48V 'A' feed using a series 100k resistor. The voltage on this pin is compared with the voltage on the FEEDB pin internally by the supply arbitration logic to determine which voltage will be used. 19 I DRAIN SENSE The DRAIN SENSE input monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. An internal 10µA source pulls the DRAIN SENSE signal towards the 5V_CAP level. DRAIN SENSE must be held below 2.5V to enable the PUPX outputs. 20 O 5V_CAP External capacitor input used to filter the device’s internal operating supply. Also a hold Capacitor to sequence down and to filter any power glitches. 21 O VGATE_HS The VGATE_HS output activates an external power MOSFET switch. This signal controls inrush current by modulating the gate of the Hot Swap MOSFET device. It supplies a programmable current output which allows easy adjustment of the MOSFET turn-on slew rate. 22 O VGATEB This pin controls the gate of the active FET on FEEDB. 23 O VGATEA This pin controls the gate of the active FET on FEEDA 24 PWR V12 This is the positive supply input. An internal shunt regulator limits the voltage on this pin to approximately 12V with respect to VSS. A resistor must be placed in series with the V12 pin to limit the regulator current (RD in the application schematics). 25 I FBD Active-high, logic level input that can be used to indicate when the converter controlled by PUPD is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. See Figures 5 and 6. 26 I FBC Active-high, logic level input that can be used to indicate when the converter controlled by PUPC is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. See Figures 5 and 6. 27 I FBB Active-high, logic level input that can be used to indicate when the converter controlled by PUPB is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. See Figures 5 and 6. 28 I FBA Active-high, logic level input that can be used to indicate when the converter controlled by PUPA is fully powered. A hold-off timer allows the secondary side (which is not powered up initially) to control shut down via an opto- isolator. See Figures 5 and 6. |
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同様の説明 - SMH4814SCR01 |
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