GS1574A Data Sheet

33416 - 5

March 2006

4 of 16

9

VEE_D

Analog

Power

Most negative power supply for the digital circuitry and output buffer.

Connect to GND.

10, 11

SDO, SDO

Analog

Output

Equalized serial digital differential output.

12

VEE_D

Analog

Power

Most negative power supply for the digital circuitry and output buffer.

Connect to GND.

13

VCC_D

Analog

Power

Most positive power supply for the digital I/O pins of the device.

Connect to +3.3V DC.

14

MUTE

Not

Synchronous

Input

CONTROL SIGNAL INPUT

levels are LVCMOS/LVTTL compatible. (3.3V Tolerant)

When the MUTE pin is set HIGH by the application interface, the serial

digital output of the device will be forced to a steady state.

When the MUTE pin is set LOW, the serial digital output of the device

will be active.

NOTE: This pin may be connected directly to the CD pin to allow mute

on loss of carrier.

15

CD

Not

Synchronous

Output

STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Indicates the presence of a good input signal.

When the CD pin is LOW, a good input signal has been detected.

When this pin is HIGH, the input signal is invalid.

This pin will indicate loss of carrier for data rates > 19Mb/s.

16

VCC_A

Analog

Power

Most positive power supply for the analog circuitry of the device.

Connect to +3.3V DC.

–

Center Pad

–

Power

Internally bonded to VEE_A.

Table 1-1: GS1574A Pin Descriptions (Continued)

Pin Number

Name

Timing

Type

Description