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SI3018-X-FS データシート(PDF) 1 Page - Silicon Laboratories

部品番号 SI3018-X-FS
部品情報  GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT
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メーカー  SILABS [Silicon Laboratories]
ホームページ  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI3018-X-FS データシート(HTML) 1 Page - Silicon Laboratories

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Rev. 1.05 6/05
Copyright © 2005 by Silicon Laboratories
Si3056
Si3056
Si3018/19/10
GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT
Features
Complete DAA includes the following:
Applications
Description
The Si3056 is an integrated direct access arrangement (DAA) with a
programmable line interface to meet global telephone line requirements. Available
in two 16-pin small outline packages, it eliminates the need for an analog front end
(AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The
Si3056 dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The Si3056
interfaces directly to standard modem DSPs.
Functional Block Diagram
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
80 dB dynamic range TX/RX paths
Integrated codec and 2- to 4-wire
hybrid
Integrated ring detector
Type I and II caller ID support
Line voltage monitor
Loop current monitor
Polarity reversal detection
Programmable digital gain
Clock generation
Pulse dialing support
Overload detection
3.3 V power supply
Direct interface to DSPs
Serial interface control for up to eight
devices
>5000 V isolation
Proprietary isolation technology
Parallel handset detection
+3.2 dBm TX/RX level mode
Programmable digital hybrid for near-
end echo reduction
Low-profile SOIC packages
Lead-free/RoHS-compliant packages
available
V.92 modems
Voice mail systems
Multi-function printers
Set-top boxes
Fax machines
Internet appliances
Personal digital
assistants
Isolation
Interface
Hybrid and
dc
Termination
Ring Detect
Off-Hook
Isolation
Interface
Digital
Interface
Control
Interface
Si3056
Si3018/19/10
QE2
QE
QB
RNG2
RNG1
DCT3
DCT2
VREG2
VREG
DCT
SC
IB
RX
MCLK
SCLK
FSYNC
SDI
SDO
FC/RGDT
RGDT/FSD/M1
OFHK
M0
RESET
AOUT/INT
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
Ordering Information
See page 88.
Pin Assignments
Si3056
Si3018/19/10
FC/RGDT
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
MCLK
FSYNC
SCLK
V
D
SDO
SDI
RESET
OFHK
RGDT/FSD/M1
M0
V
A
GND
AOUT/INT
C1A
C2A
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
DCT2
IGND
DCT3
QB
QE2
SC
VREG2
RNG2
QE
DCT
RX
IB
C1B
C2B
VREG
RNG1


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