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SI8250 データシート(PDF) 6 Page - Silicon Laboratories |
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SI8250 データシート(HTML) 6 Page - Silicon Laboratories |
6 / 30 page Si8250/1/2 6 Preliminary Rev. 0.8 Table 4. ADC0 (12-Bit ADC) Specifications TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified. Parameter Conditions Min Typ Max Units DC Accuracy Resolution — 12 — bits Integral Nonlinearity — — ±2 LSB Differential Nonlinearity Guaranteed Monotonic — — ±1 LSB Offset Error — ±3 — LSB Full Scale Error Differential mode — 3 — LSB Offset Temperature Coefficient — TBD — ppm/°C Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion — 64 — dB Total Harmonic Distortion Up to the 5th harmonic — 83 — dB Spurious-Free Dynamic Range — –73 — dB Conversion Rate Conversion Time in SAR Clocks Note 1 — 13 — clocks Track/Hold Acquisition Time Note 2 1 — — µs Throughput Rate — — 200 ksps Analog Inputs Input Voltage Range 0 — VREF V Input Capacitance — 15 — pF Temperature Sensor Linearity Notes 3, 4 — ±TBD — °C Gain Notes 3, 4 — 1353 — µV/°C Offset Notes 3, 4 (Temp = 0 °C) — 488 — mV Power Specifications Power Supply Current (VDD sup- plied to ADC0) Operating Mode, 200 ksps — 780 — µA Power-On Time After VREF settle, before tracking begins —5 — µs Power Supply Rejection — TBD — mV/V Notes: 1. An additional 2 FCLK cycles are required to start and complete a conversion. 2. Additional tracking time may be required depending on the output impedance connected to the ADC input. 3. Represents one standard deviation from the mean. 4. Includes ADC offset, gain, and linearity variations. |
同様の部品番号 - SI8250 |
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同様の説明 - SI8250 |
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