TSC87C52

8

Rev. C – 10 Sept 1997

Preliminary

MATRA MHS

When in mode 2 and 3 (9–bit mode), RI flag is set during stop bit if framing error is enabled or during ninth bit if not

(see Figure 5).

RI

TI

RB8

TB8

REN

SM2

SM1

SM0/FE

IDL

PD

GF0

GF1

POF

–

SMOD0

SMOD1

To UART framing error control

SM0 to UART mode control

Set FE bit if stop bit is 0 (framing error)

Figure 3 Framing error block diagram

Data byte

RI

SMOD0=X

Stop

bit

Start

bit

RXD

D7

D6

D5

D4

D3

D2

D1

D0

FE

SMOD0=1

Figure 4 Enhanced UART timing diagram in mode 1

RI

SMOD0=0

Data byte

Ninth

bit

Stop

bit

Start

bit

RXD

D8

D7

D6

D5

D4

D3

D2

D1

D0

RI

SMOD0=1

FE

SMOD0=1

Figure 5 Enhanced UART timing diagram in mode 2 and 3

Table 4 SCON – Serial Control Register (98h)

765432

10

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

Symbol

Description

FE

SM0

Framing Error bit (SMOD0 bit set)

Set by hardware when an invalid stop bit is detected.

Clear to reset the error state, not cleared by a valid stop bit.

Serial Mode bit 0 (SMOD0 bit cleared)

Used with SM1 to select serial mode.

SM1

Serial Mode bit 1

Used with SM0 to select serial mode.

SM2

Multiprocessor Communication Enable bit

Set to enable multiprocessor communication feature in mode 2 and 3.

Clear to disable multiprocessor communication feature.