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ES35P40-75CG2Y データシート(PDF) 1 Page - Excel Semiconductor Inc. |
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ES35P40-75CG2Y データシート(HTML) 1 Page - Excel Semiconductor Inc. |
1 / 35 page ES I ES I 1 Rev. 0D May 11 , 2006 ES25P40 Excel Semiconductor inc. ADVANCED INFORMATION ES25P40 4Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface ARCHITECTURAL ADVANTAGES • Single power supply operation - 2.7V -3.6V for read and program operations • Memory Architecture - Eight sectors with 512 Kb each • Program - Page program ( up to 256 bytes) in 1.5ms (typical) - Program cycles are on a page by page basis •Erase - 0.5s typical sector erase time - 3s typical bulk erase time • Endurance - 100,000 cycles per sector (typical) • Data Retention - 20 years (typical) • Parameter Page - 256 Byte page independent from main memory for parameter storage - Seperate from array, erase time < 20ms • Device ID - JEDEC standard two-byte electronic signature - RES instruction one-byte electronic signature for backward compatibility - Manufacturer and device type ID • Process Technology - Manufactured on 0.18um process technology • Package Option - Industry Standard Pinouts - 8-pin SO (208mil) package - All Pb-Free devices are RoHS Compliant PERFORMANCE CHARACTERISTICS •Speed - 75Mhz clock rate (maximum) • Power Saving Standby Mode - Standby mode 50uA (max) - Deep Power Down Mode 1uA (typical) MEMORY PROTECTION FEATURES • Memory Protection - W# pin works in conjunction with Status Register Bits to protect specified memory areas - Status Register Block Protection Bits (BP2, BP1, BP0) in status register configure parts of memory as read only SOFTWARE FEATURES • SPI Bus Compatible Serial Interface |
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同様の説明 - ES35P40-75CG2Y |
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