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PT7313E データシート(PDF) 6 Page - Princeton Technology Corp

部品番号 PT7313E
部品情報  Stereo Audio Processor for Car Audio
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メーカー  PTC [Princeton Technology Corp]
ホームページ  http://www.princeton.com.tw
Logo PTC - Princeton Technology Corp

PT7313E データシート(HTML) 6 Page - Princeton Technology Corp

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PT7313E
V1.0
6
February 2010
ACKNOWLEDGE
During the Acknowledge clock pulse (ACK), the SDA output port of the master device (
μP) would be sets on Hi-Z state,
if peripheral device (ex : audio processor) recognize the I
2C command the SDA line will be pull-down by slave device
during the SCL clock pulse held in HIGH state period. Please refer to the diagram below. The slave device that has been
addressed to generate an Acknowledge after receiving each byte, otherwise, the SDA Line will remain at the High level
in period of the ninth (9th) clock pulse. In this case, the host controller will generate a STOP sign in order to abort the
transfer mission.
TRANSMISSION WITHOUT ACKNOWLEDGE
If the application does not need to verify the Acknowledge signal that generated by the slave device is right or not, host
controller can just bypass the acknowledge check and transmit next data byte to the slave device. If this approach is
used, there are greater chances of faulty operation as well as decrease in noise immunity.
INTERFACE PROTOCOL
The interface protocol sequence was defined in below section:
• A Start sign
• A Chip Address of the desire slave device. The W Bit must be “0” (written). The PT7313E will always response an
Acknowledge on the end of each byte.
• A Data Sequence (N-Bytes + Acknowledge)
• A Stop Condition
PT7313E Address
MSB
First Byte
LSB
MSB
LSB MSB
LSB
START
1 0 0 0 1 0 0 W ACK
DATA
ACK
DATA
ACK
STOP
Chip Address
Data Transmitting (N-Bytes + Acknowledge)
ACK=Acknowledge
PT7313E CHIP ADDRESS
The PT7313E chip address is 88H AND binary table is shown on below.
MSB
LSB
1
0
0
0
1
0
0
0


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