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GS820H32AT データシート(PDF) 11 Page - GSI Technology |
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GS820H32AT データシート(HTML) 11 Page - GSI Technology |
11 / 23 page Rev: 1.04 3/2000 11/23 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. E GS820H32AT/Q-150/138/133/117/100/66 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ. 4. Device is deselected as defined by the Truth Table. AC Test Conditions Parameter Conditions Input high level 2.3V Input low level 0.2V Input slew rate 1V/ns Input reference level 1.25V Output reference level 1.25V Output load Fig. 1& 2 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD -1uA 1uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0V ≤ V IN ≤ V IH -1uA -1uA 1uA 300uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0V ≤ V IN ≤ V IL -300uA -1uA 1uA 1uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD -1uA 1uA Output High Voltage VOH IOH = - 8mA, VDDQ=2.375V 1.7V Output High Voltage VOH IOH = -8mA, VDDQ=3.135V 2.4V Output Low Voltage VOL IOL = 8mA 0.4V DQ VT=1.25V 50 Ω 30pF* DQ 2.5V Output Load 1 Output Load 2 225 Ω 225 Ω 5pF* * Distributed Test Jig Capacitance |
同様の部品番号 - GS820H32AT |
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同様の説明 - GS820H32AT |
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