74ABTH16841ADL datasheet(5/10 Pages) PHILIPS

部品番号	74ABTH16841ADL

部品情報	20-bit bus interface latch 3-State

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メーカー	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product specification

74ABT16841A

74ABTH16841A

20-bit bus interface latch (3-State)

1998 Feb 27

5

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Tamb = +25°C

Tamb = -40°C

to +85

°C

UNIT

Min

Typ

Max

Min

Max

VIK

Input clamp voltage

VCC = 4.5V; IIK = -18mA

–0.9

–1.2

V

VCC = 4.5V; IOH = -3mA; VI = VIL or VIH

2.5

2.9

2.5

V

VOH

High-level output voltage

VCC = 5.0V; IOH = -3mA; VI = VIL or VIH

3.0

3.4

3.0

V

VCC = 4.5V; IOH = -32mA; VI = VIL or VIH

2.0

2.4

2.0

V

VOL

Low-level output voltage

VCC = 4.5V; IOL = 64mA; VI = VIL or VIH

0.42

0.55

V

VRST

Power-up output voltage3

VCC = 5.5V; IO = 1mA; VI = GND or VCC

0.13

0.55

V

Input leakage current

II

In ut leakage current

74ABT16841A

VCC = 5.5V; VI = VCC or GND

±0.01

±1

±1.0

µA

I

74ABT16841A

CC

I

CC

µ

Input leakage current

VCC = 5.5V; VI = VCC or GND

Control pins

±0.01

±1

µA

II

Input leakage current

74ABTH16841A

VCC = 5.5V; VI = VCC

Data pins5

0.01

1

µA

74ABTH16841A

VCC = 5.5V; VI = 0

Data ins5

–2

–3

–5

µA

Bus Hold current inputs6

VCC = 4.5V; VI = 0.8V

35

IHOLD

Bus Hold current inputs6

74ABTH16841A

VCC = 4.5V; VI = 2.0V

–75

µA

74ABTH16841A

VCC = 5.5V; VI = 0 to 5.5V

±800

IOFF

Power-off leakage current

VCC = 0.0V; VO or VI ≤ 4.5V

±5.0

±100

µA

IPU/PD

Power-up/down 3-State

output current4

VCC = 2.1V; VO = 0.5V; VI = GND or VCC;

VOE = Don’t care

±5.0

±50

µA

IOZH

3-State output High current

VCC = 5.5V; VO = 2.7V; VI = VIL or VIH

5.0

10

µA

IOZL

3-State output Low current

VCC = 5.5V; VO = 0.5V; VI = VIL or VIH

–5.0

–10

µA

ICEX

Output High leakage current

VCC = 5.5V; VO = 5.5V; VI = GND or VCC

5.0

50

µA

IO

Output current1

VCC = 5.5V; VO = 2.5V

–50

–70

–180

–50

–180

mA

ICCH

VCC = 5.5V; Outputs High, VI = GND or VCC

0.5

1

mA

ICCL

Quiescent supply current

VCC = 5.5V; Outputs Low, VI = GND or VCC

10

19

mA

ICCZ

VCC = 5.5V; Outputs 3-State; VI = GND or VCC

0.5

1

mA

∆ICC

Additional supply current per

input pin2

VCC = 5.5V; one input at 3.4V, other inputs at

VCC or GND

0.2

1

mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a

transition time of up to 100

µsec is permitted.

5. Unused pins at VCC or GND.

6. This is the bus hold overdrive current required to force the input to the opposite logic state.

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL

PARAMETER

WAVEFORM

Tamb = +25oC

VCC = +5.0V

Tamb = -40 to +85oC

VCC = +5.0V ±0.5V

UNIT

MIN

TYP

MAX

MIN

MAX

tPLH

tPHL

Propagation delay

nDx to nQx

2

1.1

1.5

3.1

2.2

4.1

3.1

1.1

1.5

4.9

3.6

ns

tPLH

tPHL

Propagation delay

nLE to nQx

1

1.5

1.0

2.5

2.1

3.3

2.8

1.5

1.0

3.7

3.1

ns

tPZH

tPZL

Output enable time

to High and Low level

4

5

1.2

2.4

2.2

3.2

2.9

1.2

4.0

3.6

ns

tPHZ

tPLZ

Output disable time

from High and Low level

4

5

1.8

1.5

3.0

2.5

4.0

3.2

1.8

1.5

4.9

3.7

ns

同様の部品番号 - 74ABTH16841ADL

メーカー	部品番号	データシート	部品情報
NXP Semiconductors	74ABTH16821A	80Kb / 10P	20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State 1998 Feb 27
	74ABTH16821ADGG	80Kb / 10P	20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State 1998 Feb 27
	74ABTH16821ADL	80Kb / 10P	20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State 1998 Feb 27
	74ABTH16823A	86Kb / 12P	18-bit bus interface D-type flip-flop with reset and enable 3-State 1998 Feb 27
	74ABTH16823ADGG	86Kb / 12P	18-bit bus interface D-type flip-flop with reset and enable 3-State 1998 Feb 27

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