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GS880F18T-11 データシート(PDF) 1 Page - GSI Technology |
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GS880F18T-11 データシート(HTML) 1 Page - GSI Technology |
1 / 25 page Rev: 1.03 3/2000 1/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N Preliminary GS880F18/36T-10/11/11.5/12/14 512K x 18, 256K x 36 8Mb Sync Burst SRAMs 10ns - 14ns 3.3V VDD 3.3V & 2.5V I/O 100 Pin TQFP Commercial Temp Industrial Temp Features • Flow through mode operation. • 3.3V +10%/-5% Core power supply. • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Internal Self-Timed Write cycle. • Automatic power-down for portable applications. • 100-lead TQFP package Functional Description Applications The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. Controls Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Designing For Compatibility The JEDEC Standard for Burst RAMS calls for a FT mode pin option (pin 14 on TQFP). Board sites for Flow through Burst RAMS should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI’s Pipeline/Flow through configurable Burst RAMS or any vendor’s Flow through or configurable Burst SRAM. Bumps designed with the FT pin location tied High or floating must employ a non-configurable Flow through Burst RAM, like this RAM, to achieve Flow through functionality. 88018/32/36T Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS880F18/32/36T operates on a 3.3V power supply and all inputs/outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. -10 -11 -11.5 -12 -14 Flow Through 2-1-1-1 tKQ tCycle IDD 10ns 10ns 225mA 11ns 15ns 180mA 11.5ns 15ns 180mA 12ns 15ns 180mA 14ns 15ns 175mA |
同様の部品番号 - GS880F18T-11 |
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同様の説明 - GS880F18T-11 |
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