データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

GS840Z36AGT-150I データシート(PDF) 6 Page - GSI Technology

部品番号 GS840Z36AGT-150I
部品情報  4Mb Pipelined and Flow Through Synchronous NBT SRAMs
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS840Z36AGT-150I データシート(HTML) 6 Page - GSI Technology

Back Button GS840Z36AGT-150I Datasheet HTML 2Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 3Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 4Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 5Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 6Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 7Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 8Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 9Page - GSI Technology GS840Z36AGT-150I Datasheet HTML 10Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 24 page
background image
GS840Z18/36AT-180/166/150/100
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
6/24
© 2001, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Function
W
BA
BB
BC
BD
Read
H
X
X
X
X
Write Byte “a”
L
L
H
H
H
Write Byte “b”
L
H
L
H
H
Write Byte “c”
L
H
H
L
H
Write Byte “d”
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H


同様の部品番号 - GS840Z36AGT-150I

メーカー部品番号データシート部品情報
logo
GSI Technology
GS84018 GSI-GS84018 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018AB-100 GSI-GS84018AB-100 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018AB-100I GSI-GS84018AB-100I Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018AB-150 GSI-GS84018AB-150 Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84018AB-150I GSI-GS84018AB-150I Datasheet
911Kb / 31P
   256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
More results

同様の説明 - GS840Z36AGT-150I

メーカー部品番号データシート部品情報
logo
GSI Technology
GS841Z18AT GSI-GS841Z18AT Datasheet
655Kb / 30P
   4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS842Z18AB GSI-GS842Z18AB Datasheet
722Kb / 30P
   4Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18T-V GSI-GS8320Z18T-V Datasheet
1,013Kb / 23P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8321Z18E GSI-GS8321Z18E Datasheet
1Mb / 34P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8160Z36DGT-200I GSI-GS8160Z36DGT-200I Datasheet
246Kb / 24P
   18Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS880Z18T-100 GSI-GS880Z18T-100 Datasheet
404Kb / 25P
   8Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8160Z36DGT-250IV GSI-GS8160Z36DGT-250IV Datasheet
240Kb / 23P
   18Mb Pipelined and Flow Through Synchronous NBT SRAMs
GS8320Z18T GSI-GS8320Z18T Datasheet
463Kb / 24P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
logo
List of Unclassifed Man...
GS882Z18B-100 ETC-GS882Z18B-100 Datasheet
802Kb / 34P
   8Mb Pipelined and Flow Through Synchronous NBT SRAMs
logo
GSI Technology
GS8320ZV18T GSI-GS8320ZV18T Datasheet
606Kb / 23P
   36Mb Pipelined and Flow Through Synchronous NBT SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com