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GS840F36AGT-8.5 データシート(PDF) 7 Page - GSI Technology

部品番号 GS840F36AGT-8.5
部品情報  256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS840F36AGT-8.5 データシート(HTML) 7 Page - GSI Technology

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GS840F18/32/36AT-7.5/8/8.5/10/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.09 10/2004
7/21
© 1999, GSI Technology
Note:
There is a pull-up device on the LBO pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
HHHH
1
Write byte A
H
L
L
HHH
2, 3
Write byte B
HLHLH
H
2, 3
Write byte C
H
L
H
H
L
H
2, 3, 4
Write byte D
H
L
HHH
L
2, 3, 4
Write all bytes
H
LLLLL
2, 3, 4
Write all bytes
L
XXXX
X
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00


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