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GS880E32BGT-333 データシート(PDF) 11 Page - GSI Technology

部品番号 GS880E32BGT-333
部品情報  512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS880E32BGT-333 データシート(HTML) 11 Page - GSI Technology

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GS880E18/32/36BT-333/300/250/200/150
Rev: 1.02 10/2004
11/28
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
WR
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.


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