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GS840H32AT-180 データシート(PDF) 5 Page - GSI Technology |
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GS840H32AT-180 データシート(HTML) 5 Page - GSI Technology |
5 / 30 page GS840H18/32/36AT/B-180/166/150/100 Rev: 1.11 10/2004 5/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. TQFP Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BW I Byte Write—Writes all enabled bytes; active low BA, BB I Byte Write Enable for DQA, DQB Data I/’s; active low BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E1, E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC - No Connect |
同様の部品番号 - GS840H32AT-180 |
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同様の説明 - GS840H32AT-180 |
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