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GS8170DD36C データシート(PDF) 6 Page - GSI Technology |
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GS8170DD36C データシート(HTML) 6 Page - GSI Technology |
6 / 29 page GS8170DD36C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 6/29 © 2002, GSI Technology, Inc. Special Functions Burst Cycles SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. SigmaRAM DDR Burst Read with Counter Wrap-around Counter Wraps QA2 QA3 QA0 QA1 QA2 QA3 QB0 QB1 ADV B3 A2 B0 CQ DQ /E1 /W XX Internal Address A2 A0 B2 B1 A3 Continue A1 A3 B1 B0 CK XX Read Continue External Address A2 XX XX Continue Read |
同様の部品番号 - GS8170DD36C |
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同様の説明 - GS8170DD36C |
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