Preliminary

GS8182D18D-250/200/167

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 11/2004

11/27

© 2003, GSI Technology

State Diagram

Power-Up

Read NOP

Load New

Read Address

R Count = 0

DDR Read

R Count = R Count + 1

Write NOP

Load New

Write Address

W Count = 0

DDR Write

W Count = W Count + 1

WRITE

READ

READ

R Count = 2

WRITE

W Count = 2

READ

WRITE

Always

Always

READ

R Count = 2

Notes:

1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.

2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is

true for “WRITE” and “WRITE”.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

5. R Count is the read counter; Burst of 4 must complete 2 DDR reads.

6. W Count is the write counter; Burst of 4 must complete 2 DDR writes.

READ

R Count = 1

Always

Increment

Read Address

WRITE

W Count = 2

Increment

Write Address

WRITE

W Count = 1

Always