Preliminary

GS8182Q18D-200/167/133

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 11/2004

6/28

© 2003, GSI Technology

Burst of 2 SigmaQuad-II SRAM DDR Write

The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of

K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is

clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on

the rising edge of K along with the write address. A high on W causes a write port deselect cycle.

Burst of 2 Double Data Rate SigmaQuad-II SRAM Write First

Special Functions

Byte Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Write A

Read B

Read C Write D

NOP

Read E Write F

Read G Write H

NOP

A

B

C

D

E

F

G

H

A

A+1

D

D+1

F

F+1

H

H+1

B

B+1

C

C+1

E

E+1

G

K

K

Address

R

W

BWx

D

C

C

Q

CQ

CQ