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GS8182Q18D-133I データシート(PDF) 7 Page - GSI Technology

部品番号 GS8182Q18D-133I
部品情報  18Mb Burst of 2 SigmaQuad-II SRAM
Download  28 Pages
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8182Q18D-133I データシート(HTML) 7 Page - GSI Technology

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Preliminary
GS8182Q18D-200/167/133
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 11/2004
7/28
© 2003, GSI Technology
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample
Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written
Unchanged
Unchanged
Written


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