データシートサーチシステム |
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GS8321E18GE-225 データシート(PDF) 8 Page - GSI Technology |
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GS8321E18GE-225 データシート(HTML) 8 Page - GSI Technology |
8 / 34 page GS8321E18/32/36E-250/225/200/166/150/133 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03 4/2005 8/34 © 2003, GSI Technology Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB Note: There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00011011 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11000110 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00011011 2nd address 01 00 11 10 3rd address 10110001 4th address 11100100 Burst Counter Sequences BPR 1999.05.18 |
同様の部品番号 - GS8321E18GE-225 |
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同様の説明 - GS8321E18GE-225 |
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