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GS81032AT-5I データシート(PDF) 11 Page - GSI Technology |
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GS81032AT-5I データシート(HTML) 11 Page - GSI Technology |
11 / 23 page Rev: 1.01 7/2001 11/23 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS81032AT/Q-150/138/133/117/100/66 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ, and tOHZ. 4. Device is deselected as defined by the Truth Table. AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V Output load Fig. 1& 2 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0 V ≤ V IN ≤ V IL –300 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA, VDDQ = 2.375 V 1.7V — Output High Voltage VOH IOH = –4 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 4 mA — 0.4 V DQ VT = 1.25 V 50 Ω 30pF* DQ 2.5 V Output Load 1 Output Load 2 225 Ω 225 Ω 5pF* * Distributed Test Jig Capacitance |
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同様の説明 - GS81032AT-5I |
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