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GS815018AB-250 データシート(PDF) 6 Page - GSI Technology

部品番号 GS815018AB-250
部品情報  1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
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メーカー  GSI [GSI Technology]
ホームページ  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS815018AB-250 データシート(HTML) 6 Page - GSI Technology

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Register-Register Late Write, Pipelined Read Truth Table
CK
ZZ
SS
SW
Bx
G
Current Operation
DQ
(tn)
DQ
(tn+1)
X
1
X
X
X
X
Sleep (Power Down) mode
Hi-Z
Hi-Z
0
1
X
X
X
Deselect
***
Hi-Z
0
0
1
X
1
Read
Hi-Z/
Hi-Z
0
0
1
X
0
Read
***
Q(tn)
0
0
0
0
X
Write All Bytes
***
D(tn)
0
0
0
X
X
Write Bytes with Bx = 0
***
D(tn)
0
0
0
1
X
Write (Abort)
***
Hi-Z
Notes:
1. If one or more Bx = 0, then B = “T” else B = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”.
3. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
GS815018/36AB-357/333/300/250
Product Preview
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 10/2005
6/25
© 2003, GSI Technology


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