データシートサーチシステム |
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GS816032BGT-200IV データシート(PDF) 7 Page - GSI Technology |
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GS816032BGT-200IV データシート(HTML) 7 Page - GSI Technology |
7 / 23 page Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB GS8160xxBT-xxxV Preliminary Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01 5/2006 7/23 © 2004, GSI Technology Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Burst Counter Sequences BPR 1999.05.18 |
同様の部品番号 - GS816032BGT-200IV |
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同様の説明 - GS816032BGT-200IV |
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