Philips Semiconductors

Product specification

74ABT843

9-bit bus interface latch with set and reset

(3-State)

1998 Jan 16

3

LOGIC SYMBOL

13

14

LE

PRE

11

1

MR

OE

23

45

67

89

10

D0 D1 D2 D3 D4 D5 D6 D7 D8

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

23 22 21 20 19 18 17 16 15

SA00251

LOGIC SYMBOL (IEEE/IEC)

223

322

421

520

619

718

817

916

13

14

10

15

11

1

1D

EN

R

S2

C1

SA00252

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

OE

PRE

MR

LE

Dn

Qn

L

L

X

X

X

H

Preset

L

H

L

X

X

L

Clear

L

L

H

H

H

H

H

H

L

H

L

H

Transparent

L

L

H

H

H

H

↓

↓

l

h

L

H

Latched

H

X

X

X

X

Z

High impedance

L

H

H

L

X

NC

Hold

H = High voltage level

h

= High voltage level one set-up time prior to the High-to-Low LE transition

L

= Low voltage level

l

= Low voltage level one set-up time prior to the High-to-Low LE transition

NC= No change

X = Don’t care

Z = High impedance “off” state

↓ = High-to-Low transition