74ALVCH16821DL datasheet(7/12 Pages) PHILIPS

部品番号	74ALVCH16821DL

部品情報	20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

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Philips Semiconductors

Product specification

74ALVCH16821

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

1998 May 29

7

AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE

GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF

LIMITS

SYMBOL

PARAMETER

WAVEFORM

VCC = 2.5V ± 0.2V

UNIT

MIN

TYP1

MAX

tPLH/tPHL

Propagation delay

nCP to nQn

1, 4

1.0

2.6

5.8

ns

tPZH/tPZL

3-State output enable time

nOEn to nQn

2, 4

1.0

2.8

6.6

ns

tPHZ/tPLZ

3-State output disable time

nOEn to nQn

2, 4

1.0

2.2

5.7

ns

tW

nCP pulse width HIGH or LOW

3, 4

3.0

1.8

ns

tSU

Set up time nDn to nCP

3, 4

1.4

0.3

ns

th

Hold time nDn to nCP

3, 4

0.4

0.0

ns

Fmax

Maximum clock pulse frequency

1, 4

150

250

MHz

NOTE:

1. All typical values are at VCC = 2.5V and Tamb = 25°C.

AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF

LIMITS

SYMBOL

PARAMETER

WAVEFORM

VCC = 3.3 ± 0.3V

VCC = 2.7V

UNIT

MIN

TYP1

MAX

MIN

TYP1

MAX

tPHL/tPLH

Propagation delay

nCP to nQn

1, 4

1.0

2.5

4.5

1.0

2.8

5.3

ns

tPZH/tPZL

3-State output enable time

nOEn to nQn

2, 4

1.0

2.3

5.1

1.0

3.2

6.2

ns

tPHZ/tPLZ

3-State output disable time

nOEn to nQn

2, 4

1.0

2.8

4.6

1.0

3.1

5.0

ns

tW

nCP pulse width HIGH or

LOW

3, 4

3.3

0.2

3.3

1.7

ns

tSU

Set up time nDn to nCP

3, 4

1.0

0.2

1.2

0.3

ns

th

Hold time nDn to nCP

3, 4

0.8

0.4

0.6

–0.3

ns

Fmax

Maximum clock pulse

frequency

1, 4

150

350

150

300

MHz

NOTES:

1. All typical values are at Tamb = 25°C.

同様の部品番号 - 74ALVCH16821DL

メーカー	部品番号	データシート	部品情報
Texas Instruments	74ALVCH16821DLG4	312Kb / 12P	[Old version datasheet] 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Texas Instruments	74ALVCH16821DLRG4	312Kb / 12P	[Old version datasheet] 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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