74F50109 datasheet(2/12 Pages) PHILIPS

部品番号	74F50109

部品情報	Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics

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メーカー	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product specification

74F50109

Synchronizing dual J–K positive edge-triggered

flip-flop with metastable immune characteristics

2

September 14, 1990

853-1388 00422

FEATURE

• Metastable immune characteristics

• Output skew guaranteed less than 1.5ns

• High source current (I

OH = 15mA) ideal for clock driver

applications

• Pinout compatible with 74F109

• See 74F5074 for synchronizing dual D-type flip-flop

• See 74F50728 for synchronizing cascaded D-type flip-flop

• See 74F50729 for synchronizing dual D-type flip-flop with

edge-triggered set and reset

TYPE

TYPICAL fmax

TYPICAL SUPPLY

CURRENT( TOTAL)

74F50109

150MHz

22mA

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE

DESCRIPTION

VCC = 5V ±10%,

PKG DWG #

Tamb = 0°C to +70°C

16–pin plastic DIP

N74F50109N

SOT38-4

16–pin plastic SO

N74F50109D

SOT109-1

INPUT AND OUTPUT LOADING

AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/

LOW

LOAD

VALUE

HIGH/LOW

J0, J1

J inputs

1.0/0.417

20

µA/250µA

K0, K1

K inputs

1.0/0.417

20

µA/250µA

CP0, CP1

Clock inputs

(active rising edge)

1.0/0.033

20

µA/20µA

SD0, SD1

Set inputs

(active low)

1.0/0.033

20

µA/20µA

RD0, RD1

Reset inputs

(active low)

1.0/0.033

20

µA/20µA

Q0, Q1, Q0, Q1

Data outputs

750/33

15mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the high

state and 0.6mA in the low state.

PIN CONFIGURATION

GND

VCC

SD1

Q1

CP1

RD1

J1

RD0

J0

CP0

SD0

Q0

16

15

14

13

12

11

10

7

6

5

4

3

2

1

9

8

K1

K0

SF00598

LOGIC SYMBOL

J1

J0

Q0 Q0 Q1 Q1

VCC = Pin 16

GND = Pin 8

CP0

SD0

RD0

CP1

SD1

RD1

4

5

1

12

11

15

K1

K0

2 14

3 13

6

7

10

9

SF00599

IEC/IEEE SYMBOL

6

7

1J

2J

C1

C2

R

1K

2K

R

S

10

9

2

4

3

1

5

14

12

13

15

11

SF00600

同様の部品番号 - 74F50109

メーカー	部品番号	データシート	部品情報
NXP Semiconductors	74F50728	89Kb / 12P	Synchronizing cascaded dual positive edge-triggered D-type flip-flop 1990 Sep 14
	74F50729	94Kb / 12P	Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics 1990 Sep 14
	74F5074	92Kb / 12P	Synchronizing dual D-type flip-flop/clock driver 1990 Sep 14

More results

同様の説明 - 74F50109

メーカー	部品番号	データシート	部品情報
NXP Semiconductors	74ABT5074	131Kb / 13P	Synchronizing dual D-type flip-flop with metastable immune characteristics 2002 Dec 17
	74ABT5074	100Kb / 7P	Synchronizing dual D-type flip-flop with metastable immune characteristics 2002 Dec 17
	74F50729	94Kb / 12P	Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics 1990 Sep 14
Fairchild Semiconductor	DM74ALS109A	55Kb / 6P	Dual J-K Positive-Edge-Triggered Flip-Flop
NXP Semiconductors	74ALS109A	93Kb / 9P	Dual J-K positive edge-triggered flip-flop with set and reset 1991 Feb 08
NXP Semiconductors	74ALS112A	92Kb / 10P	Dual J-K negative edge-triggered flip-flop 1991 Feb 08
Texas Instruments	SN74F112NSR	627Kb / 13P	[Old version datasheet] DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
NXP Semiconductors	74F112	83Kb / 10P	Dual J-K negative edge-triggered flip-flop 1990 Feb 09
NXP Semiconductors	74F50728	89Kb / 12P	Synchronizing cascaded dual positive edge-triggered D-type flip-flop 1990 Sep 14
Mitsubishi Electric Sem...	M74LS73AP	220Kb / 4P	DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET