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74HCT107DB データシート(PDF) 4 Page - NXP Semiconductors |
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74HCT107DB データシート(HTML) 4 Page - NXP Semiconductors |
4 / 7 page December 1990 4 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107 Fig.4 Functional diagram. Fig.5 Logic diagram (one flip-flop). FUNCTION TABLE Note 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition X = don’t care ↓ = HIGH-to-LOW CP transition OPERATING MODE INPUTS OUTPUTS nRnCP J K Q Q asynchronous reset L X X X L H toggle H ↓ hh qq load “0” (reset) H ↓ Ih L H load “1” (set) H ↓ hI H L hold “no change” H ↓ II q q |
同様の部品番号 - 74HCT107DB |
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同様の説明 - 74HCT107DB |
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