December 1990

10

Philips Semiconductors

Product specification

Quad D-type flip-flop; positive-edge trigger;

3-state

74HC/HCT173

AC WAVEFORMS

Fig.6

Waveforms showing the clock (CP) to

pulse width, the output transition times and

the maximum clock pulse frequency.

Fig.7

Waveforms showing the master reset (MR)

propagation delays and the master reset to

clock (CP) removal time.

Fig.8

Waveforms showing the 3-state enable and

disable times.

PACKAGE OUTLINES

See

Fig.9 Waveforms showing the data set-up and hold

The shaded areas indicate when the input is permitted to

change for predictable output performance.