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M27C4002-70J1TR データシート(PDF) 9 Page - STMicroelectronics

部品番号 M27C4002-70J1TR
部品情報  4 Mbit (256Kb x16) UV EPROM and OTP EPROM
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M27C4002-70J1TR データシート(HTML) 9 Page - STMicroelectronics

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M27C4002
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C4002s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C4002 may be common. A TTL low level
pulse applied to a M27C4002's E input, with VPP
at 12.75V, will program that M27C4002. A high
level E input inhibits the other M27C4002s from
being programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at VIL,E at VIH,VPP at 12.75V and VCC at 6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVEL
VALID
AI00730
A0-A17
Q0-Q15
VPP
VCC
G
DATA IN
DATA OUT
E
tQVEL
tVPHEL
tVCHEL
tEHQX
tELEH
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 7. Programming Flowchart
AI00726C
n = 0
Last
Addr
VERIFY
E = 100
µs Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO


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