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74HCT251PW データシート(PDF) 2 Page - NXP Semiconductors |
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74HCT251PW データシート(HTML) 2 Page - NXP Semiconductors |
2 / 7 page December 1990 2 Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 FEATURES • True and complement outputs • Both outputs are 3-state for further multiplexer expansion • Multifunction capability • Permits multiplexing from n-lines to one line • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT251 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT251 are the logic implementations of single-pole 8-position switches with the state of three select inputs (S0,S1,S2) controlling the switch positions. Assertion (Y) and negation (Y) outputs are both provided. The output enable input (OE) is active LOW. The logic function provided at the output, when activated, is: Y= OE.(I0.S0.S1.S2 + I1.S0.S1.S2 + + I2.S0.S1.S2 + I3.S0.S1.S2 + + I4.S0.S1.S2 + I5.S0.S1.S2 + + I6.S0.S1.S2 + I7.S0.S1.S2) Both outputs are in the high impedance OFF-state (Z) when the output enable input is HIGH, allowing multiplexer expansion by tying the outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V In to Y 15 19 ns In to Y17 19 ns Sn to Y 20 20 ns Sn to Y21 21 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 44 46 pF |
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同様の説明 - 74HCT251PW |
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