データシートサーチシステム |
|
74HC4040D データシート(PDF) 1 Page - NXP Semiconductors |
|
74HC4040D データシート(HTML) 1 Page - NXP Semiconductors |
1 / 24 page 1. General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. 2. Features s Multiple package options s Complies with JEDEC standard no. 7A s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specified from −40 °Cto+85 °C and from −40 °C to +125 °C 3. Applications s Frequency dividing circuits s Time delay circuits s Control counters 4. Quick reference data 74HC4040; 74HCT4040 12-stage binary ripple counter Rev. 03 — 14 September 2005 Product data sheet Table 1: Quick reference data GND = 0 V; Tamb =25 °C; tr =tf = 6 ns. Symbol Parameter Conditions Min Typ Max Unit Type 74HC4040 tPHL, tPLH propagation delay CP to Q0 CL = 15 pF; VCC = 5 V - 14 - ns Qn to Qn+1 CL = 15 pF; VCC =5V - 8 - ns |
同様の部品番号 - 74HC4040D |
|
同様の説明 - 74HC4040D |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |